library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity codeConverter1 is
   port( SW    :     IN    std_logic_vector  (  1  downto   0  );
         hex   :     OUT   std_logic_vector  (  6  downto   0  ) );
end codeConverter1;

architecture behavioural of codeConverter1 is
begin
   process( SW )
   begin
      case SW is
         when "00" => hex <= "1000000";
         when "01" => hex <= "1111001";
         when "10" => hex <= "0100100";
         when others => hex <= "0110000";
      end case;
   end process;
end behavioural;


